Samsung noted that its 3nm process node used 45% less power while also giving 23% more performance. These are small, yet have a flexible design to adjust the power channel width per customer needs, said Samsung, without revealing how the chips are currently being mass-produced.
Samsung’s 3nm Process Node
The world’s largest memory chip maker and the second-largest contract chipmaker – Samsung, began making chips based on its newest 3nm process node. The South Korean giant has already been competing sharply with TSMC, who’s having more prominent clients in its portfolio. Thus, Samsung pledged to spend $355 billion over the next five years to improve its movements in the semiconductor industry, which is called a strategic business. In this pursuit, Samsung announced commencing mass chip production based on the advanced 3nm process node. The company said this process node used 45% less power when compared to the current-best 5nm process node, offering 23% more performance and 16% reduced surface area. It uses the Multi-Bridge-Channel FET (MBCFET) – a gate-all-around (GAA) transistor architecture that makes the channels wider to allow electricity to flow better and reduce the voltage level – making it better than the FinFET transistor architecture. Though Samsung didn’t mention for whom it’s mass-producing the chips, it said the 3nm process node design is so flexible that it can adjust the channel width per customer needs. Also, a second-generation 3nm node is in the pipeline, the company noted, with more improved improvements, surface area and power usage.
